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data sheet 2.5v differential lvds clock divider and fanout buffer 8t74s208a-01 8t74s208a-01 revision 2 08/17/16 1 ?2016 integrated device technology, inc. general description the 8t74s208a-01 is a high-performance differential lvds clock divider and fanout buffer. the device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. the 8t74s208a-01 is characterized to operate from a 2.5v power supply. guaranteed output-to-output and part-to-part skew characteristics make the 8t74s208a-01 ideal for those clock distribution applications dem anding well-defined performance and repeatability. the integrated i nput termination resistors make interfacing to the reference source easy and reduce passive component count. each output can be individually enabled or disabled in the high-impedance state controlled by a i 2 c register. on power-up, all outputs are disabled. features one differential input reference clock differential pair can accept the following differential input levels: lvds, lvpecl, cml integrated input termination resistors eight lvds outputs selectable clock frequency di vision of 1, 2, 4 and 8 maximum input clock frequency: 1ghz lvcmos interface levels for the control inputs individual output enabled/ disabled by i 2 c interface output skew: 45ps (maximum) output rise/fall ti mes: 370ps (maximum) low additive phase jitter, rms: 96fs (typical) full 2.5v supply voltage outputs disable at power up lead-free (rohs 6) 32-lead vfqfn packaging -40c to 85c ambient operating temperature block diagram pin assignment 8t74s208a-01 32-lead vfqfn, 5mm x 5mm x 0.925mm f ref i 2 c 2 2 in nin v t fsel[1:0] sda scl adr[1:0] pullup pullup pulldown (2) pulldown (2) 50 ? 50 ? 1, 2, 4, 8 8 q0 nq0 q1 nq1 q2 nq2 q3 nq3 q4 nq4 q5 nq5 q6 nq6 q7 nq7 q1 32 1 v ddo v ddo q2 adr0 nq2 q3 nq3 q4 nq4 q5 nq5 gnd q6 nq6 q7 nq7 gnd fsel0 scl in fsel1 nin v t sda v dd gnd nq1 q1 nq0 q0 gnd adr1 8t74s208a-01 2 3 4 5 6 7 8 9 10111213141516 24 23 22 21 20 19 18 17 31 30 29 28 27 26 25 refer to pcn# n1608-01, effe ctive date november 18, 2016 for new designs use p art number 8t74s208c-01
8t74s208a-01 data sheet 2.5v differential lvds clock divider an d fanout buffer 2 revision 2 08/17/16 pin descriptions and pin characteristics table 1. pin descriptions 1 note 1: pulldown and pullup refer to internal i nput resistors. see table 2 , pin characteristics, for typical values. number name type description 1 adr1 input pulldown i 2 c address input. lvcmos/lvttl interface levels. 2 gnd power ground pin. 3q0output differential output pair 0. lvds interface levels. 4 nq0 output 5q1output differential output pair 1. lvds interface levels. 6 nq1 output 7 gnd power ground pin. 8 v ddo power output supply pin. 9q2output differential output pair 2. lvds interface levels. 10 nq2 output 11 q3 output differential output pair 3. lvds interface levels. 12 nq3 output 13 q4 output differential output pair 4. lvds interface levels. 14 nq4 output 15 q5 output differential output pair 5. lvds interface levels. 16 nq5 output 17 v ddo power output supply pin. 18 gnd power ground pin. 19 q6 output differential output pair 6. lvds interface levels. 20 nq6 output 21 q7 output differential output pair 7. lvds interface levels. 22 nq7 output 23 gnd power ground pin. 24 fsel0 input pulldown frequency divider select control. see table 3a for function. ? lvcmos/lvttl interface levels. 25 fsel1 input pulldown frequency divider select control. see table 3a for function. ? lvcmos/lvttl interface levels. 26 in input non-inverting differential clock input. rt = 50 ? termination to v t. 27 v t termination input input for termination. both in and ni n inputs are internally terminated 50 ? to this pin. see input termination information in the applications section. 28 nin input inverting differential clock input. rt = 50 ? termination to v t. 29 v dd power power supply pin. 30 sda i/o pullup i 2 c data input/output. input. lv cmos/lvttl interface levels. ? output: open drain. 31 scl input pullup i 2 c clock input. lvcmos/lvttl interface levels. 32 adr0 input pulldown i 2 c address input. lvcmos/lvttl interface levels.
revision 2 08/17/16 3 2.5v differentia l lvds clock divider and fanout buffer 8t74s208a-01 data sheet table 2. pin characteristics symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2 pf r pulldown input pulldown resistor 51 k ? r pullup input pullup resistor 51 k ?
8t74s208a-01 data sheet 2.5v differential lvds clock divider an d fanout buffer 4 revision 2 08/17/16 function tables input frequency divider operation the fsel1 and fsel0 control pins configure the input frequency divider. in the default state (fsel[1:0] are set to logic 0:0 or left open) the output frequency is equal to the input frequency (divide-by-1). the other fsel[1:0] settings configure the input divider to divide-by-2, 4 or 8, respectively. output enable operation the output enable/disable state of each individual differential output qx, nqx can be set by the content of the i 2 c register (see table 3c ). a logic zero to an i 2 c bit in register 0 enables the corresponding differential output, while a logic one disables the differential output (see table 3b ). after each power cycle, the device resets all i 2 c bits (dn) to its default state (logic 1) and all qx, nqx outputs are disabled. after the first valid i 2 c write, the output enabl e state is controlled by the i 2 c register. setting and changing the output enable state through the i 2 c interface is asynchronous to the input reference clock. i 2 c interface protocol the 8t74s208a-01 uses an i 2 c slave interface for writing and reading the device configuratio n to and from the on-chip configuration registers. this device uses the standard i 2 c write format for a write transaction, and a standard i 2 c read format for a read transaction. figure 1 defines the i 2 c elements of the standard i 2 c transaction. these elements consis t of a start bit, data bytes, an acknowledge or not-acknowledge bit and the stop bit. these elements are arranged to make up the complete i 2 c transactions as shown in figure 1 and figure 2 . figure 1 is a write transaction while figure 2 is read transaction. the 7-bit i 2 c slave address of the 8t74s208a-01 is a combination of a 5-bit fixed addresses and two variable bits which are set by the hardware pins adr[1:0] (binary 11010, adr1, adr0). bit 0 of slave address is used by the bus controller to select either the r ead or write mode. the hardware pins adr1 and adr0 and should be individually set by the user to avoid address conflicts of multiple 8t 74s208a-01 devices on the same bus. figure 1. standard i 2 c transaction start (s) ? defined as high-to-low transition on sda while holding scl high. data ? between start and stop cycl es, sda is synchronous with scl. data may change only when scl is low and must be stable when scl is high. acknowledge (a) ? sda is driven low before the scl rising edge and held low until the scl falling edge. stop (s) ? defined as low-to-high transition on sda while holding scl high figure 2. read transaction figure 3. read transaction s ? start or repeated start w ? r/w is set for write r ? r/w is set for read a ?ack devadd ?7 bit device address p ? stop table 3a. fsel[1:0] input selection function table 1 note 1: fsel1, fsel0 are asynchronous controls input operation fsel1 fsel0 0 (default) 0 (default) f q[7:0] = f ref 1 01f q[7:0] = f ref 2 10f q[7:0] = f ref 4 11f q[7:0] = f ref 8 table 3b. individual output enable control bit operation dn 0 output qx, nqx is enabled. 1 (default) output qx, nqx is disabled in high-impedance state. table 3c. individual output enable control bit d7d6d5d4d3d2d1d0 output q7 q6 q5 q4 q3 q2 q1 q0 default11111111 table 3d. i 2 c slave address 7654321 0 1 1 0 1 0 adr1 adr0 r/w s cl s da start valid data acknowledge stop swa ap devadd data byte sra ap devadd data byte
revision 2 08/17/16 5 2.5v differentia l lvds clock divider and fanout buffer 8t74s208a-01 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to t he device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc electrical characteristics or ac electrical characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage, v cc 4.6v inputs, v i -0.5v to v dd + 0.5v input termination current, i vt 35ma outputs, i o continuous current surge current 10ma 15ma storage temperature, t stg -65 q c to 150 qc maximum junction temperature, tj max 125c esd - human body model 1 2000v esd - charged device model 1 500v dc electrical characteristics . item rating note 1: according to jedec/js-001-2012/jesd22-c101e. table 4a. power supply dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v dd power supply voltage 2.375 2.5v 2.625 v v ddo output supply voltage 2.375 2.5v 2.625 v i dd power supply current 41 49 ma i ddo output supply current all outputs are enabled and terminated 153 176 ma table 4b. lvcmos/lvttl input dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typic al maximum units v ih input high voltage 1 fsel[1:0], adr[1:0] v dd = 2.5v 5% 1.7 v cc + 0.3v v scl, sda v dd = 2.5v 5% 1.9 v cc + 0.3v v v il input low voltage 1 fsel[1:0], adr[1:0] v dd = 2.5v 5% -0.3 0.7 v scl, sda v dd = 2.5v 5% -0.3 0.5 v i ih input high current fsel[1:0], adr[1:0] v dd = v in = 2.625 150 a scl, sda v dd = v in = 2.625 5 a i il input low current fsel[1:0], adr[1:0] v dd = 2.625, v in = 0v -10 a scl, sda v dd = 2.625, v in = 0v -150 a note 1: v il should not be lower than -0.3v and v ih should not be higher than v dd + 0.3v.
8t74s208a-01 data sheet 2.5v differential lvds clock divider an d fanout buffer 6 revision 2 08/17/16 . table 4c. differential input dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v in input voltage swing 1 note 1: v il should not be less than -0.3v and v ih should not be greater than v dd. in, nin 0.15 1.2 v v cmr common mode input voltage 1, 2 note 2: common mode input voltage is defined as the cross point. 1.2 v dd ? (v pp /2) v v diff differential input voltage swing in, nin 0.3 2.4 v r in input resistance in, ? nin to v t 40 50 60 ? r in, d iff differential input resistance in to nin, ? v t = open 80 100 120 ? table 4d. lvds dc characteristics, v dd = v ddo = 2.5v, t a = -40c to 85c symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 247 454 mv ? v od v od magnitude change 50 mv v os offset voltage 1.120 1.425 v ? v os v os magnitude change 50 mv
revision 2 08/17/16 7 2.5v differentia l lvds clock divider and fanout buffer 8t74s208a-01 data sheet ac electrical characteristics table 5. ac electrical characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c 1 note 1: electrical parameters are guarante ed over the specified ambient operating tem perature range, which is established when t he device is mounted in a test socket with maintained transverse ai rflow greater than 500 lfpm. the device will meet specification s after thermal equilibrium has been reached under these conditions. symbol parameter test conditio ns minimum typical maximum units f ref input frequency in, nin 1ghz f scl i 2 c clock frequency 400 khz t jit buffer additive phase jitter, rms; refer to additive phase jitter section, measured with fsel[1:0] = 00 f ref =156.25, integration range: 12khz ? 20mhz 96 120 fs t pd propagation delay 2 note 2: measured from the differential input cr osspoint to the differential output crosspoint. in, nin to ? qx, nqx fsel[1:0] = 00 420 620 ps fsel[1:0] = 01 580 800 ps fsel[1:0] = 10 680 920 ps fsel[1:0] = 11 780 1050 ps t sk(o) output skew 3, 4 note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at the differential crosspoint. note 4: this parameter is defined in accordance with jedec standard 65. 45 ps t sk(p) pulse skew fsel[1:0] = 00 55 ps t sk(pp) part-to-part skew 4, 5, 6 note 5: defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same freque ncy and with equal load conditions. using the sa me type of inputs on each device, the outputs are measured at the differential cros - spoint. note 6: part-to-part skew specif ication does not guarantee divider synchronization among devices. 200 ps odc output duty cycle 7 note 7: if fsel[1:0] = 00 (divide-by-one), the out put duty cycle will depend on the input duty cycle. fsel[1:0] = 00 50 % fsel[1:0] = 01 48 50 52 % fsel[1:0] = 10 48 50 52 % fsel[1:0] = 11 48 50 52 % t pdz output enable and ? disable time 8 note 8: measured from sda rising edge of i 2 c stop command. output enable/ disable state from/ to active/ inactive 1s t r / t f output rise/ fall time 20% to 80% 155 230 ps 10% to 90% 245 350 ps
8t74s208a-01 data sheet 2.5v differential lvds clock divider an d fanout buffer 8 revision 2 08/17/16 additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of t he fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specifi ed, the phase noise is called a dbc value, which simply means dbm at a specif ied offset from the fundamental. by investigating jitter in the fr equency domain, we get a better understanding of its effects on the de sired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. typical phase jitter at 156.25mhz ssb phase noise (dbc/hz) offset from carrier frequency (hz) additive phase: 96fs (typical) the input source is 156.25mhz wenzel oscillator.
revision 2 08/17/16 9 2.5v differentia l lvds clock divider and fanout buffer 8t74s208a-01 data sheet parameter measur ement information lvds output load ac test circuit part-to-part skew pulse skew differential input level output skew output rise/fall time v dd , v ddo nqx qx nqy qy t sk(pp) part 1 part 2 t plh t phl tsk(p) = |t phl - t plh | nin in nqy qy nin in v dd gnd v cmr cross points v in nqx qx nqy qy 20% 80% 80% 20% t r t f v od nqx qx 10% 90% 90% 10% t r t f v od nqx qx
8t74s208a-01 data sheet 2.5v differential lvds clock divider and fanout buffer 10 revision 2 08/17/16 parameter measurement information, continued propagation delay single-ended & differential input voltage swing offset voltage setup output duty cycle/pulse width/period differential output voltage setup nqx qx nin in t pd v in v diff_in differential voltage swing = 2 x single-ended v in nin in nqx qx
revision 2 08/17/16 11 2.5v different ial lvds clock divider and fanout buffer 8t74s208a-01 data sheet applications information differential input with built-in 50 ? termination interface the in /nin with built-in 50 ? terminations accept lvds, lvpecl, cml and other differential signals. both differential signals must meet the v in and v cmr requirements. figure 4a to figure 4c show interface examples for the in/nin input with built-in 50 ? terminations driven by the most common driv er types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination reco mmendation. please consult with the vendor of the driver component to confirm the driv er termination requirements. figure 4a. in/nin input with built-in 50 ? driven by an lvds driver figure 4b. in/nin input with built-in 50 ? driven by a cml driver with open collector figure 4c. in/nin input with built-in 50 ? driven by an lvpecl driver 2.5v lvd s 3.3v or 2.5v 50 50 in nin vt rec eiv er w ith built-in 50 zo = 50 zo = 50 2.5v 2.5v in nin vt rec eiv er with built-in 50 zo = 50 zo = 50 50 50 cml ? open collector 2.5v lvpecl 2.5v 50 50 in nin vt rec eiv er w ith built-in 50 zo = 50 zo = 50 r1 18
8t74s208a-01 data sheet 2.5v differential lvds clock divider and fanout buffer 12 revision 2 08/17/16 vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 5 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?h eat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further informatio n, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 5. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) recommendations for unused input and output pins i nputs: lvcmos control pins all control pins have internal pullup or pulldown resistors; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be ei ther left floating or terminated with 100 ? across. if they are left floating, there should be no trace attached. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
revision 2 08/17/16 13 2.5v different ial lvds clock divider and fanout buffer 8t74s208a-01 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical poi nt-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 6a can be used with either type of output structure. figure 6b , which can also be used with both output type s, is an optional te rmination with center tap capacitance to help filter comm on mode noise. the capacitor value should be approximately 50pf. if us ing a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. figure 6a. standard lvds termination figure 6b. optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
8t74s208a-01 data sheet 2.5v differential lvds clock divider and fanout buffer 14 revision 2 08/17/16 power considerations 1. power dissipation. the total power dissipation for the 8t74s208a-01 is the sum of th e core power plus the power dissipated due to the load. the fo llowing is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. ? power (core) max = v dd_max * i dd_max = 2.625v * 49ma = 128.625mw ? power (output) max = v ddo_max * i ddo = 2.625v * 176ma = 462mw ? power dissipation for internal termination r t with v t floating ? power (r t ) max = (v in_max ) 2 / r t_min = (1.2) 2 / 80 = 18mw total power_ max = (3.465v, with all outputs swit ching) = 128.625 + 462mw + 18mw = 608.625mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad direct ly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (e xample calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the approp riate value is 42.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.61w * 42.7c/w = 111c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depe nding on the number of loaded ou tputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32-lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard te st boards 42.7c/w 37.3c/w 33.5c/w
revision 2 08/17/16 15 2.5v different ial lvds clock divider and fanout buffer 8t74s208a-01 data sheet reliability information transistor count the transistor count for 8t74s208a-01 is 5,910. table 7. ? ja vs. air flow table for a 32-lead vfqfn ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 42.7c/w 37.3c/w 33.5c/w
8t74s208a-01 data sheet 2.5v differential lvds clock divider and fanout buffer 16 revision 2 08/17/16 32-lead vfqfn package out line and package dimensions
revision 2 08/17/16 17 2.5v different ial lvds clock divider and fanout buffer 8t74s208a-01 data sheet 32-lead vfqfn package outline an d package dimensions, continued
8t74s208a-01 data sheet 2.5v differential lvds clock divider and fanout buffer 18 revision 2 08/17/16 ordering information note: parts that are ordered with an ?g? su ffix to the part number are the pb-fr ee configuration and are rohs compliant. revision history] revision date description of change august 17, 2016 table 8. ordering information part/order number marking package shipping packaging temperature 8t74s208a-01nlgi idt8t74s208a-01nlgi ?lead-free? 32-lead vfqfn tray -40 q c to 85 qc 8T74S208A-01NLGI8 idt8t74s208a-01nlgi ?lead-free? 32-lead vfqfn tape & reel -40 q c to 85 qc ?
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